The present invention is related to a semiconductor integrated circuit and suitably used for a semiconductor integrated circuit with a layout based on a TSV bump technique, in which a plurality of TSV (through silicon via) bumps arrayed in a matrix, such as a wide I/O (input/output) and a HBM (high bandwidth memory).
Recently, there exists an increasing demand of mobile DRAMs (dynamic random access memories) with a lower power consumption and a higher data transmission rate in applications to smart phones, slate type or tablet type personal computers (PCs) and the like. There are two generally known techniques for increasing the data transmission rate of a memory; one is to increase the operation frequency of the input/output bus and the other is to enlarge the bit width of the input/output bus. The use of the technique of increasing the data transmission rate by increasing the operation frequency, such as LPDDR (low power double data rate) type memories, however, may result in an increase in the power consumption.
A technique called wide I/O is known in the art in connection with LPDDR. In a wide I/O, the total number of input/output pins is increased to increase the width of the input/output bus; this allows keeping a high data transmission rate and reducing power consumption, with a lower operation frequency.
An implementation of a wide I/O technique basically requires silicon chip stacking in which circuits are electrically connected each other via TSVs formed through the stacked semiconductor substrates. Accordingly, the positions of input/output pads of a DRAM and a SOC (system on chip) device should be aligned. The arrangement of input/output pads in the wide I/O region is standardized by JEDEC (Joint Electron Devices Engineering Council).
FIG. 1A is an example of the structure of a stack of serially-connected silicon chips. In the structure example shown in FIG. 1A, a plurality of DRAM silicon chips each having an elemental device 351 and an interconnection layer 352 are stacked. These silicon chips are connected via micro bumps 351 and TSVs 356. There silicon chips are electrically connected to an interconnection layer 354 of an SoC device 353 via via-contacts provided through the SoC device 353. The SoC device 353 is mounted on a package substrate 355 which have bumps 363.
As disclosed in non-patent literature 1 (the JEDEC standard, entitled “wide I/O single data rate”, JESD 229, December 2011), JEDEC (or Solid State Technology Association) has standardized the arrangement coordinates and definitions of the input/output pads of the wide I/O region connected to an SoC device or a DRAM. FIG. 1B is a plan view illustrating an example of the structure in which I/O buffers are located under bumps arranged in a TSV array region. FIG. 1B illustrates a region in which TSV bumps and buffers (denoted by numeral 901) are arranged in a rectangular matrix as well as a region in which ESD protection circuitries 902 and a PLL circuitry 903 are arranged.
The arrangement of TSV bumps and I/O buffers connected to input/output pads standardized by JEDEC is disclosed as a SoC floor plan of a wide I/O in non-patent literature 2 (proceedings of Mobile Memory Forum: LPDDR3 and Wide I/O, which is held on Jul. 24, 2011 in Korea).
In connection with non-patent literatures 1 and 2, a structure is known in which a main VDD power line is connected to a TSV bump via a P-channel ESD (electrostatic discharge) protection element and a main VSS power line is connected to the TSV bump via an N-channel ESD protection element.
Patent literature 1 (JP 2010-135391 A) discloses a structure in which P-channel and N-channel ESD protection elements are disposed at adjacent two sides of a TSV bump and a pre-amplifier circuitry of an I/O buffer is disposed between the P-channel and N-channel ESD protection elements.